Many years ago computer designers realized that the integrity of data processing operations could best be verified by performing the same operations at the same time utilizing duplicated equipment. This concept was implemented as early as the late 1940's in a data processing machine called the EDVAC. This machine utilized duplicated arithmetic units and the outputs of the arithmetic units were compared at the end of each operation.
Later systems such as the arrangement disclosed in U.S. Pat. No. 3,471,686 issued on Oct. 7, 1969 J. B. Connell elaborated upon this matching scheme and discovered that data matching could be benefically performed on multiple data sources during different time intervals within a single machine cycle.
J. P. Caputo et al. U.S. Pat. No. 3,770,948, issued Nov. 6, 1973, discloses another prior art diagnostic arrangement in which comparisons are made between the outputs of data handling circuits. In this arrangement, a pair of data selectors supply sets of pairs of signals to be compared by a comparator.
Concurrent with the development of more sophisticated matching techniques for data processing units, substantial strides have also been made in the area of memory diagnostics. For example, G. J. Barlow discloses a prior art memory diagnostic arrangement in his U.S. Pat. No. 3,789,204, issued Jan. 29, 1974, in which a first parity generator provides a parity indication for a memory address while a second parity generator provides another parity indication for the data to be stored at this address. These two parity indications are combined by an EXCLUSIVE OR gate and the resulting parity bit is written into memory along with the data. When information is accessed from the memory, a third parity generator, which Barlow calls a parity checker, generates a parity indication over the retrieved data. The parity indication over the address is combined with the retrieved parity bit, which represents the parity over the data and address, to generate another parity indication just over the data. This parity indication just over the data is then compared with the generated parity for the data. This arrangement appears to be useful in detecting memory and addressing faults susceptible of being detected by utilization of a single parity bit. However, the arrangement is complicated in that three separate parity generators are required and these generators only perform diagnostic operations directly related to memory accesses.
It is an object of this invention to effectively and economically perform bus comparisons and memory diagnostics utilizing the same parity generators.
It is a further object of this invention to reduce the number of parity generators required for memory diagnostics.